Semiconductor Device and Method

ABSTRACT

A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. application Ser. No.16/225,854, filed Dec. 19, 2018, which application is a continuation ofU.S. application Ser. No. 14/622,420, filed Feb. 13, 2015, now U.S. Pat.No. 10,163,709, issued on Dec. 25, 2018, which applications are herebyincorporated herein by reference.

BACKGROUND

Semiconductor devices are generally manufactured by utilizing asemiconductor substrate and manufacturing devices either within or ontop of the semiconductor substrate. Once these devices are manufactured,the individual devices are electrically connected by manufacturing oneor more metallization layers over the individual devices and over thesemiconductor substrate. These one or more metallization layers maycomprise conductive layers separated by dielectric layers that connectthe individual devices not only to each other but also to externaldevices.

However, the individual semiconductor dies are not manufacturedindividually. Rather, multiple semiconductor dies are formed on a singlesemiconductor wafer. Once the dies have been formed, the semiconductorwafer is singulated such that the individual dies are separated fromeach other and may be utilized separately.

Unfortunately, the process of singulation is fraught with potentialhazards that can have disastrous consequences. Physical and thermalstresses that may be involved in the separation of the individual diescan damage the individual dies as they are being separated, renderingthem defective and, in a worst case, inoperable.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 illustrates a first semiconductor device, a second semiconductordevice, and a third semiconductor device within and on a semiconductorsubstrate, in accordance with some embodiments.

FIG. 2 illustrates a placement of a photoresist over the semiconductorsubstrate, in accordance with some embodiments.

FIG. 3 illustrates a patterning of the semiconductor substrate throughthe photoresist, in accordance with some embodiments.

FIGS. 4A-4B illustrate a removal of the photoresist, in accordance withsome embodiments.

FIG. 5 illustrates a placement of a protective layer, in accordance withsome embodiments.

FIG. 6 illustrates a singulation of the semiconductor substrate, inaccordance with some embodiments.

FIG. 7 illustrates a bonding of the first semiconductor device, thesecond semiconductor device, and the third semiconductor device to asemiconductor wafer, in accordance with some embodiments.

FIG. 8 illustrates a thinning of the first semiconductor device, thesecond semiconductor device, and the third semiconductor device, inaccordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

With reference now to FIG. 1, there is illustrated a first wafer 101with a first semiconductor device chip 103, a second semiconductordevice chip 105, and a third semiconductor device chip 107 formed withinthe first wafer 101. In an embodiment the first wafer 101 comprises afirst substrate 109, a first active device layer 111, firstmetallization layers 113, a first passivation layer 114, and firstcontact pads 115. The first substrate 109 may comprise bulk silicon,doped or undoped, or an active layer of a silicon-on-insulator (SOI)substrate. Generally, an SOI substrate comprises a layer of asemiconductor material such as silicon, germanium, silicon germanium,SOI, silicon germanium on insulator (SGOI), or combinations thereof.Other substrates that may be used include multi-layered substrates,gradient substrates, glass substrates, ceramic substrates, or hybridorientation substrates.

The first active device layer 111 may comprise a wide variety of activedevices and passive devices such as transistors, capacitors, resistors,inductors and the like that may be used to generate the desiredstructural and functional desires of the design for the first wafer 101.The active devices within the first wafer 101 may be formed using anysuitable methods either within or else on the first substrate 109.

The first metallization layers 113 are formed over the first substrate109 and the active devices within the first active device layer 111 andmay be used to interconnect, e.g., the active devices within the firstactive device layer 111. In an embodiment the first metallization layers113 are formed of alternating layers of dielectric and conductivematerial and may be formed through any suitable process (such asdeposition, damascene, dual damascene, etc.). In an embodiment there maybe four layers of metallization, but the precise number of layers ofdielectric and conductive material is dependent upon the design of thefirst semiconductor device chip 103, the second semiconductor devicechip 105, and the third semiconductor device chip 107.

The first passivation layer 114 may be made of one or more suitabledielectric materials such as silicon oxide, silicon nitride, low-kdielectrics such as carbon doped oxides, extremely low-k dielectricssuch as porous carbon doped silicon dioxide, a polymer such aspolyimide, combinations of these, or the like. The first passivationlayer 114 may be formed through a process such as chemical vapordeposition (CVD), although any suitable process may be utilized, and mayhave a thickness between about 0.5 μm and about 5 μm, such as about 9.25KÅ.

The first contact pads 115 may be formed over and in electrical contactwith the first metallization layers 113 in order to provide externalconnections for the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107. The first contact pads 115 are formed of a conductive material suchas aluminum, although other suitable materials, such as copper,tungsten, or the like, may alternatively be utilized. The first contactpads 115 may be formed using a process such as CVD, although othersuitable materials and methods may alternatively be utilized. Once thematerial for the first contact pads 115 has been deposited, the materialmay be shaped into the first contact pads 115 using, e.g., aphotolithographic masking and etching process.

In an embodiment the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107 are formed within the first wafer 101 and are separated by scriberegions (represented in FIG. 1 by the dashed lines labeled 117) alongwhich the first wafer 101 will be separated to form the individual firstsemiconductor device chip 103, the second semiconductor device chip 105,and the third semiconductor device chip 107. The scribe regions 117 areformed by not placing functional structures (such as active devices)into the area intended for the scribe regions 117. Other structures,such as test pads or dummy metals used for planarization, could beplaced into the scribe regions 117, but would not be necessary for thefunctioning of the first semiconductor device chip 103, the secondsemiconductor device 105, and the third semiconductor device chip 107once the first semiconductor device 103, the second semiconductor devicechip 105, and the third semiconductor device 107 have been separatedfrom each other. The scribe regions 117 may be formed to have a firstwidth W₁ of between about 10 μm and about 200 μm, such as about 80 μm.

FIG. 2 illustrates a placement of a photoresist 201 over the firstsemiconductor device chip 103, the second semiconductor device chip 105,and the third semiconductor device chip 107. In an embodiment thephotoresist 201 is a photosensitive material and may be placed on thefirst semiconductor device chip 103, the second semiconductor devicechip 105, and the third semiconductor device chip 107 using, e.g., aspin coating technique to a height of between about 0.5 μm and about 15μm, such as about 5 μm. Once in place, the photoresist 201 may then bepatterned by exposing the photoresist 201 to a patterned energy source(e.g., a patterned light source) so as to induce a chemical reaction,thereby inducing a physical change in those portions of the photoresist201 exposed to the patterned light source. A developer is then appliedto the exposed photoresist 201 to take advantage of the physical changesand selectively remove either the exposed portion of the photoresist 201or the unexposed portion of the photoresist 201, depending upon thedesired pattern.

In an embodiment the photoresist 201 is patterned to form first openings203 which expose the scribe regions 117. As such, the first openings 203may be formed to have the first width W₁ of the scribe regions 117, suchas by being between about 10 μm and about 150 μm, such as about 80 μm.However, any other suitable width may alternatively be utilized.

FIG. 3 illustrates that, once the photoresist 201 has been placed andpatterned over the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107, a first etching process (represented in FIG. 3 by the arrowslabeled 301) may be performed in order to extend the first openings 203through the first passivation layer 114, the first metallization layers113, the first active device layer 111, and into the first substrate109. In an embodiment the first etching process may be, e.g., one ormore reactive ion etching processes which utilize one or more etchantsto directionally etch through the first metallization layers 113, thefirst active device layer 111, and into the first substrate 109.

As such, while the precise etchants and process conditions utilized willbe at least in part dependent upon the materials chosen for each layer,in an embodiment in which the first substrate 109 is silicon, the firstetching process 301, when etching the first substrate 109, may utilizean etchant such as F-chemicals or O₂, along with, optionally, a carriergas such as argon, although any suitable etchant may alternatively beutilized.

Additionally, an RF power for the reactive ion etching may be set to bebetween about 100 W and about 4000 W, such as about 2500 W and the biaspower may be set to be between about 10 V and about 500 V, such as about200 V. Finally, the pressure of the etching chamber may be set to bebetween about 10 mTorr and about 200 mTorr, such as about 90 mTorr, andthe temperature of the process may be controlled to be between about−20° C. and about 50° C., such as about 0° C. However, these conditionsare intended to be illustrative, as any suitable etching conditions mayalternatively be utilized, and all such process conditions are fullyintended to be included within the scope of the embodiments.

In an embodiment the first etching process 301 may be utilized to extendthe first openings 203 at least partially into the first substrate 109.For example, the first etching process 301 may be utilized to extend thefirst openings 203 a first depth D₁ into the first substrate 109 ofbetween about 5 μm and about 100 μm, such as about 30 μm. However, anyother suitable depth may alternatively be utilized.

However, while the dry etch process described above may be utilized inorder to pattern the first substrate 109, this description is intendedto be illustrative only and is not intended to be limiting to theembodiments. For example, a wet etch process which may form curvedsidewalls in which the first wafer 101 is immersed within a liquidetchant such as a HF-based solution or TMAH at a temperature of betweenabout room temperature and about 80° C. for a time period of betweenabout 1 minute and about 30 minutes, may alternatively be used. Anysuitable method of patterning the first substrate 109 may be used, andall are fully intended to be included within the scope of theembodiments.

FIG. 4A illustrates a removal of the photoresist 201 and a post removalcleaning process. In an embodiment the photoresist 201 may be removedutilizing, e.g., an ashing process, whereby a temperature of thephotoresist 201 is raised until the photoresist 201 experiences athermal decomposition and may be easily removed. However, any othersuitable removal process may alternatively be utilized.

Once the ashing has been performed, the structure may be cleaned using afirst cleaning process in order to help assist in the removal of thephotoresist 201. In an embodiment the first cleaning process may includedipping the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107 into an etchant in order to ensure that any remaining portions ofthe photoresist 201 are removed from the first semiconductor device chip103, the second semiconductor device chip 105, and the thirdsemiconductor device chip 107 prior to subsequent processing. Forexample, the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107 may be dipped into an etchant such as HF for between about 1 secondand about 100 seconds, such as about 60 seconds.

FIG. 4B illustrates a top down view of the embodiment illustrated inFIG. 4A. In this embodiment the scribe regions 117 are illustratedbetween the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107. However, as can be seen in this top-down view, the first etchingprocess 301 (described above with respect to FIG. 3) may be utilized toform rounded corners (represented in FIG. 4B by the dashed circlelabeled 401) for each of the first semiconductor device chip 103, thesecond semiconductor device chip 105, and the third semiconductor devicechip 107. In a particular, embodiment in which the first semiconductordevice chip 103 may have a second width W₂ of between about 1 mm andabout 30 mm, such as about 4 mm, and a first length L₁ of between about1 mm and about 30 mm, such as about 4 mm, the curved corner may have anarc radius R₁ of between about 50 μm and about 500 μm, such as about 250μm. However, any suitable arc radius may alternatively be utilized.

By using the first etching process 301 to form the rounded corners 401at the corners of the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107, the first semiconductor device chip 103, the second semiconductordevice chip 105, and the third semiconductor device chip 107 are betterable to withstand the stresses involved during the singulation process(described further below with respect to FIG. 6). In particular, therounded corners 401 can distribute and withstand the stresses of a sawblade physically cutting and separating the first semiconductor devicechip 103, the second semiconductor device chip 105, and the thirdsemiconductor device chip 107. As such, fewer defects will occur duringthe singulation process.

FIG. 5 illustrates a placement of a protective film 501 over the firstsemiconductor device chip 103, the second semiconductor device chip 105,and the third semiconductor device chip 107 and a thinning of thebackside of the first substrate 109. In an embodiment the protectivefilm 501 may be a backgrinding tape (BG tape), which may be used toprotect the patterned side of the first substrate 109 from grindingdebris during the thinning of the first substrate 109. The protectivefilm 501 may be applied over the first openings 203 using, for example,a roller (not separately illustrated in FIG. 5).

However, while the protective film 501 is described above as a BG tape,this is intended to be illustrative and is not intended to limit theembodiments. Rather, any suitable method of protecting the patternedsurface of the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107, including the first openings 203, may alternatively be utilized.All such protective layers are fully intended to be included within thescope of the embodiments.

Once the first openings 203 have been protected, the first substrate 109is thinned utilizing, e.g., a first thinning process (represented inFIG. 5 by the rotating platen labeled 501). In an embodiment the firstwafer 101 may be thinned using, e.g., chemical mechanical polishing,whereby a combination of chemical reactants and abrasives are utilizedwith one or more grinding pads in order to remove portions of the firstsubstrate 109 opposite the first contact pads 115. However, any othersuitable process, such as a physical grinding process, one or moreetching processes, combinations of these, or the like, may alternativelybe utilized. In an embodiment the first wafer 101 is thinned to have afirst thickness T₁ after the thinning of between about 100 μm and about500 μm, such as about 200 μm.

FIG. 6 illustrates a singulation of the first wafer 101 into the firstsemiconductor device chip 103, the second semiconductor device chip 105,and the third semiconductor device chip 107. In an embodiment theprotective film 501 is initially removed and the first wafer 101 isattached to a support substrate 601 prior to the singulation. Thesupport substrate 601 may be, for example, a tape such as the commonlyknown blue tape, and works as a means to control the placement of thefirst wafer 101. As such, while the support substrate 601 is referred toherein as a tape, the support substrate 601 is not limited to tape, andmay be any other medium, such as a carrier wafer, a carrier glass, ametal plate, or a ceramic plate, that provides for the placement of thefirst wafer 101 as desired.

Once attached to the support substrate 601, the singulation may beperformed by using a saw blade (represented in FIG. 6 by the dashed boxlabeled 603) to slice through the scribe regions 117 to form secondopenings 605 through the first substrate 109 between the firstsemiconductor device chip 103, and the second semiconductor device chip105, and between the second semiconductor device chip 105 and the thirdsemiconductor device chip 107.

In an embodiment the saw blade 603 is utilized to slice the firstsubstrate 109 between the first semiconductor device chip 103 and thesecond semiconductor device chip 105, and between the secondsemiconductor device chip 105 and the third semiconductor device chip107 without removing additional material from the sidewalls of the firstopenings 203. As such, the second openings 605 may be formed to have athird width W₃ that is less than the first width W₁, such as by beingbetween about 10 μm and about 300 μm, such as about 50 μm. However, anysuitable dimension may be used for the third width W₃. Because of this,first substrate extensions 607 are left on the first semiconductordevice chip 103, the second semiconductor device chip 105, and the thirdsemiconductor device chip 107.

Additionally, as one of ordinary skill in the art will recognize,utilizing a saw blade to singulate the first wafer 101 is merely oneillustrative embodiment and is not intended to be limiting. Alternativemethods for singulating the first wafer 101, such as utilizing one ormore etches to separate the first semiconductor device chip 103, thesecond semiconductor device chip 105, and the third semiconductor devicechip 107, may alternatively be utilized. These methods and any othersuitable methods may alternatively be utilized to singulate the firstwafer 101.

FIG. 7 illustrates a bonding of the first semiconductor device chip 103,the second semiconductor device chip 105, and the third semiconductordevice chip 107 to a second wafer 701 in a chip on wafer (CoW) bondingconfiguration. The second wafer 701 may comprise a second substrate 703,a second active device layer 705, second metallization layers 707,second passivation layer 708, and second contact pads 709, which may besimilar to the first substrate 109, the first active device layer 111,the first metallization layers 113, the first passivation layer 114, andthe first contact pads 115, respectively. The second substrate 703, thesecond active device layer 705, the second metallization layers 707, thesecond passivation layer 708, and the second contact pads 709 may form afourth semiconductor device chip 711, a fifth semiconductor device chip713, and a sixth semiconductor device chip 715 (separated by secondscribe regions 717) that will be utilized to operate in conjunction withthe first semiconductor device 103, the second semiconductor device 105,and the third semiconductor device 107, respectively.

The first semiconductor device chip 103 may be bonded to the secondwafer 701 utilizing, e.g., a fusion bonding process. In an embodimentthe fusion bonding process may be initiated by performing an initialcleaning process on the second wafer 701 where the bond is desired. In aparticular embodiment the second wafer 701 may be cleaned using, e.g., awet cleaning procedure such as an SC-1 or SC-2 cleaning procedure toform a hydrophilic surface. Once cleaned, the first semiconductor devicechip 103, the second semiconductor device chip 105, and the thirdsemiconductor device chip 107 are aligned into their respective desiredpositions on the second wafer 701 and the hydrophilic surface is placedinto physical contact with the first semiconductor device chip 103, thesecond semiconductor device chip 105, and the third semiconductor devicechip 107 to begin the bonding procedure. Once the first semiconductordevice chip 103, the second semiconductor device chip 105, and the thirdsemiconductor device chip 107 have been contacted to the second wafer701, a thermal anneal may be utilized to strengthen the bonds.

However, the descriptions of the fusion bonding as described above ismerely an example of one type of process that may be utilized in orderto bond the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107 to the second wafer 701, and is not intended to be limiting upon theembodiments. Rather, any suitable bonding process may alternatively beutilized to bond the first semiconductor device chip 103, the secondsemiconductor device chip 105, and the third semiconductor device chip107 to the second wafer 701, and all such processes are fully intendedto be included within the embodiments.

FIG. 8 illustrates a second thinning process (represented in FIG. 8 bythe rotating platen labeled 801) that is utilized to remove the firstsubstrate extensions 607 from the first semiconductor device chip 103,the second semiconductor device chip 105, and the third semiconductordevice chip 107 after the first semiconductor device chip 103, thesecond semiconductor device chip 105, and the third semiconductor devicechip 107 have been bonded to the second wafer 701. In an embodiment thefirst semiconductor device chip 103, the second semiconductor devicechip 105, and the third semiconductor device chip 107 may be thinnedusing, e.g., chemical mechanical polishing, whereby a combination ofchemical reactants and abrasives are utilized with one or more grindingpads in order to remove portions of the first semiconductor device chip103, the second semiconductor device chip 105, and the thirdsemiconductor device chip 107 opposite the first contact pads 115.However, any other suitable process, such as a physical grindingprocess, one or more etching processes, combinations of these, or thelike, may alternatively be utilized. In an embodiment the firstsemiconductor device chip 103, the second semiconductor device chip 105,and the third semiconductor device chip 107 are thinned to a thicknesssufficient to remove the first substrate extensions 607, such as beingthinned to a second thickness T₂ such as between about 10 μm and about250 μm, such as about 25 μm. However, any suitable thickness mayalternatively be used.

By utilizing the first etching process 301 to pattern the scribe regions117 prior to the singulation of the first semiconductor device chip 103,the second semiconductor device chip 105, and the third semiconductordevice chip 107, the stresses from the singulation process will bebetter relaxed, and any dicing inducing debris may be minimized. Assuch, a better interface may be obtained between the first semiconductordevice chip 103, the second semiconductor device chip 105, and the thirdsemiconductor device chip 107 and the second wafer 701. As such, abetter die-wafer fusion bonding may be achieved, resulting in a strongerbond with fewer defects.

Once the first semiconductor device chip 103, the second semiconductordevice chip 105, and the third semiconductor device chip 107 have beenbonded to the second wafer 701 and thinned, additional processing may beperformed on the second wafer 701. For example, the second wafer 701 maybe singulated itself in order to form semiconductor devices ready to beused.

In accordance with an embodiment, a method of manufacturing asemiconductor device comprising forming a first opening in a firstsemiconductor wafer between a first semiconductor die and a secondsemiconductor die, the first opening having a first width parallel to amajor surface of the semiconductor wafer is provided. The semiconductorwafer is singulated to form a second opening, wherein the first openingand the second opening separate the first semiconductor die and thesecond semiconductor die, the second opening having a second widthparallel to the major surface of the semiconductor wafer that is smallerthan the first width. The first semiconductor die is thinned until thefirst semiconductor die has a straight sidewall.

In accordance with another embodiment, a method of manufacturing asemiconductor device comprising forming a first semiconductor die and asecond semiconductor die at least partially within a semiconductorsubstrate is provided. A first portion of the semiconductor substrate isremoved, wherein the first portion is located within a scribe region ofthe semiconductor substrate. A second portion of the semiconductorsubstrate is removed using a saw blade, wherein the removing the firstportion of the semiconductor substrate and the removing the secondportion of the semiconductor substrate separate the first semiconductordie from the second semiconductor die and also forms semiconductormaterial extensions on the first semiconductor die.

In accordance with yet another embodiment, method of manufacturing asemiconductor device comprising forming a first opening within a firstsemiconductor wafer between a first semiconductor die and a secondsemiconductor die, wherein the forming the first opening is performed atleast in part with an etching process is provided. A second opening isformed within the first semiconductor wafer between the firstsemiconductor die and the second semiconductor die, wherein the formingthe second opening is performed at least in part with a sawing processand wherein the second opening has a smaller width than the firstopening and the first opening and the second opening extend singulatethe first semiconductor die from the second semiconductor die. The firstsemiconductor die and the second semiconductor die are bonded to asecond semiconductor wafer. The first semiconductor die and the secondsemiconductor die are thinned after the bonding the first semiconductordie and the second semiconductor die, wherein the thinning the firstsemiconductor die and the second semiconductor die remove extensionregions from the first semiconductor die and the second semiconductordie.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of manufacturing a semiconductor device,the method comprising: partially singulating a first semiconductordevice of a semiconductor wafer from a second semiconductor device ofthe semiconductor wafer, the semiconductor wafer comprising a firstsemiconductor material; thinning the first semiconductor material afirst time and a second time different from the first time, whereinafter the thinning the first semiconductor material the second time thefirst semiconductor device has a straight sidewall, wherein the thinningthe first semiconductor material reduces a thickness from between about100 μm and 500 μm to between about 10 μm and 250 μm; and sawing thefirst semiconductor material between the thinning the firstsemiconductor material the first time and the thinning the firstsemiconductor material the second time.
 2. The method of claim 1,wherein the partially singulating the first semiconductor device formsan opening within a scribe region, the scribe region having a width ofbetween about 10 μm and about 200 μm.
 3. The method of claim 1, whereinthe partially singulating the first semiconductor device forms a roundedcorner.
 4. The method of claim 3, wherein the rounded corner has an arcradius of between about 50 μm and about 500 μm.
 5. The method of claim3, wherein the rounded corner has an arc radius of between about 50 μmand about 250 μm.
 6. The method of claim 1, wherein the partiallysingulating the first semiconductor device forms an opening into asemiconductor substrate of the semiconductor wafer to a depth of betweenabout 5 μm and about 100 μm.
 7. The method of claim 6, wherein theopening has curved sidewalls.
 8. A method of manufacturing asemiconductor device, the method comprising: a first semiconductordevice adjacent to a second semiconductor device, wherein a firstsemiconductor material extends from within the first semiconductordevice, between the first semiconductor device and the secondsemiconductor device, to within the second semiconductor device;chemical mechanical polishing the first semiconductor material to afirst thickness of between about 100 μm and about 500 μm; cutting thefirst semiconductor material after the chemical mechanical polishing thefirst semiconductor material; and after the cutting, chemical mechanicalpolishing the first semiconductor material to a second thickness ofbetween about 10 μm and about 250 μm.
 9. The method of claim 8, furthercomprising, prior to the chemical mechanical polishing the firstsemiconductor material to the first thickness, patterning the firstsemiconductor device to have a curved corner.
 10. The method of claim 9,wherein the curved corner has an arc radius of between about 50 μm andabout 250 μm.
 11. The method of claim 10, wherein the firstsemiconductor device has a first length of between about 1 mm and about30 mm and has a first width of between 1 mm and about 30 mm.
 12. Themethod of claim 9, wherein the patterning the first semiconductor devicecomprises a wet etching process.
 13. The method of claim 12, wherein thewet etching process forms curved sidewalls.
 14. The method of claim 8,wherein the first semiconductor material has a smaller thickness betweenthe first semiconductor device and the second semiconductor device thanwithin the second semiconductor device.
 15. A method of manufacturing asemiconductor device, the method comprising: manufacturing a firstsemiconductor device and a second semiconductor device with asemiconductor wafer; singulating the first semiconductor device from thesecond semiconductor device, the singulating comprising: a firstchemical mechanical polishing process; a second chemical mechanicalpolishing process; and a sawing process between the first chemicalmechanical polishing process and the second chemical mechanicalpolishing process, wherein the sawing process occurs while asemiconductor substrate of the semiconductor wafer has a thickness ofbetween about 100 μm and about 500 μm.
 16. The method of claim 15,wherein after the second chemical mechanical polishing process thesemiconductor substrate has a thickness of between about 10 μm and about250 μm.
 17. The method of claim 15, further comprising fusion bondingthe first semiconductor device to a second semiconductor wafer after thesawing process and prior to the second chemical mechanical polishingprocess.
 18. The method of claim 15, further comprising etching anopening into the semiconductor wafer prior to the first chemicalmechanical polishing process and after the manufacturing the firstsemiconductor device.
 19. The method of claim 18, wherein the openinghas a first depth into the semiconductor wafer of between about 5 μm andabout 100 μm.
 20. The method of claim 18, wherein the etching theopening forms curved sidewalls.